What is Solido?
Solido Design Automation is the leading provider of variation-aware design and characterization software, including Variation Designer and ML Characterization Suite product lines. Used by over 1000 designers at more than 40 major companies worldwide, Solido provides the world’s most advanced variation-aware design and characterization software powered by proprietary machine learning technologies. The production-proven and versatile toolset is the easiest to use in its class and unparalleled in customer responsiveness.
The importance of variation-aware design and characterization is only increasing with greater power demands, decreasing margins, and smaller and more advanced technology nodes. Managing to select better design tradeoffs and avoid product failures is a huge challenge in memory, analog/RF and standard cell IC design, but by doing so, designers produce more competitive products in shorter design cycles and with fewer respins. Solido has proven that its products are the best solution for solving real production problems, meeting the challenges of its customers in day-to-day design.
Solido’s products are positioned to continue as the most advanced design technology because of Solido’s rich culture of innovation, dedication to producing high-caliber software, and ability as an agile company to focus on the most difficult challenges faced by the industry. We work closely with our customers to push the limits of design, and continually challenge ourselves to create more efficient and inventive solutions.
Answers to some frequently asked questions about us.
What are the specific custom IC design challenges your customers are facing?
We segment the challenges our customers are facing in the following areas:
- PVT Corner design. PVT variation encompasses process (FF, SS, FS, SF, TT model corners), voltage, temperature, load and parasitic based variation. When taking all the combinations of these parameters, our customers end up having 1000’s or 10,000’s of corner combinations to simulate. The challenge is that to simulate all the corner combinations is accurate, but very slow. Guessing which corners to simulate is faster, but inaccurate.
- 3-sigma Monte Carlo design. The process model corners that foundries like TSMC or GLOBALFOUNDRIES release in their PDK’s are not well suited to individual designs. They are either overly conservative leading to overdesign, or overly optimistic leading to yield loss. As a result, foundries are now releasing local and global statistical variation models for designers to run Monte Carlo analysis simulation on their designs. However, brute force Monte Carlo SPICE simulation is slow, inefficient, and time consuming to use in the design loop.
- High-sigma Monte Carlo design. For designs that are being replicated 1000’s or more times, designing to high-sigma becomes important. Examples include bit cells for memory design or standard cell library designs. To design to 6-sigma, 5 billion Monte Carlo sample simulations would be needed that would take years and therefore impractical. Alternatively, designers are designing to 3-sigma, and extrapolating to high-sigma but this methodology is inaccurate. Some companies have developed internal importance sampling techniques, but these don’t scale and suffer from accuracy issues.
- Variation debug. If the design is failing PVT corner, 3-sigma or 6-sigma Monte Carlo verification steps, designers need to identify the design sensitivities to variation and figure out how to fix the design, making it robust to variation. Manually changing the device sizes and running PVT or Monte Carlo analysis to check whether the changes fix the design is tedious and time consuming.
- Cell optimization. Similar to variation debug where the design is failing PVT corners, 3-sigma or 6-sigma Monte Carlo verification steps, or the design is not optimized against spec, changing device sizes and running PVT or Monte Carlo analysis to check whether the design is optimal is also tedious and time consuming.
As you can see, the common theme is that the number of SPICE simulations required to get complete design coverage is exploding, which is leading designers to compromise accuracy to get their designs out sooner, or compromise design time to get accurate results.
Our customers are facing these challenges when doing memory, standard cell, lower power and analog/RF design.
What does Solido Design do?
Solido provides variation analysis and design software for custom IC’s so that our customers can achieve maximum yield and performance in their designs. Solido’s product, Variation Designer, boosts SPICE simulator efficiency while increasing design coverage. Solido Variation Designer is being used by top semiconductor companies to design memory, standard cell, analog/RF and low power custom IC designs at leading design nodes including TSMC and GLOBALFOUNDRIES 40nm, 28nm, 20nm, 16nm.
How does Solido help with your customers’ custom IC design challenges?
Our customers use the following capabilities in our Variation Designer product:
- Fast PVT. Our customers use Fast PVT to automatically figure out which are the worst case corners while simulating only a fraction of the corner combinations. This leads to far fewer simulations than brute force PVT corner analysis without compromising accuracy.
- Fast Monte Carlo. Our customers use Fast Monte Carlo to cut down the number of simulations to achieve 3-sigma design without compromising accuracy, and extract design specific 3-sigma corners to design to.
- High-Sigma Monte Carlo (HSMC). Our customers use High-Sigma Monte Carlo to get the 5 billion Monte Carlo accuracy runs in only a few thousand simulations. This is a dramatic reduction in SPICE simulations and improvement in design coverage. Solido High-Sigma Monte Carlo is fast, accurate, scalable and verifiable.
- DesignSense. Our customers use DesignSense to automatically identify design sensitivities to variation, so that users can quickly make necessary design changes and verify that it’s meeting specifications.
- Cell Optimizer. Our customers use Solido Variation Designer Cell Optimizer to automatically vary device sizes within any design and PDK sizing constraints, to optimize the design against PVT and 3-sigma to 6-sigma Monte Carlo variation.
Overall, while SPICE simulator companies are focused on improving speed, accuracy and capacity of their tools, Solido is complementarily focused on intelligently figuring out what to simulate giving better design coverage in a reduced number of simulations than brute force.
What are the tool flows your customers are using?
Our customers use Solido Variation Designer with their SPICE simulator of choice. Variation Designer is integrated with Cadence Spectre/SpectreRF/APS, Synopsys HSPICE/HSIM/FineSim/XA, Mentor Eldo, BDA AFS, Agilent GoldenGate. Through our partnership with Cadence, Solido Variation Designer is integrated with Analog Design Environment (ADE), or alternatively our customers input designs through the command line. Variation Designer is integrated with Platform LSF, Oracle Grid Engine and Runtime Design Automation NetworkComputer to run 10’s or 100’s of simulators in parallel. Finally, Solido is qualified in the TSMC, GLOBALFOUNDRIES and STARC reference flows for variation analysis and design.
What is the roadmap for Solido?
We’ve developed a rich custom IC design software platform:
- Through our vendor partnerships, we have robust integration with design environments, SPICE simulators and cluster distribution tools.
- Through our foundry partnerships, we have rich PDK integration to read corner, local and global statistical variation and insight into variation effects at advanced nodes.
- By working closely with our customers, we have developed algorithmic engines in support of user tasks that dramatically reduce the number of simulations without compromising accuracy.
Going forward we will continue to work with customers and foundries to address advanced node custom IC design challenges. Having a custom IC design software platform allows us to build new capabilities very quickly and efficiently by leveraging our existing software integrations and enhancing, adapting and inventing algorithmic engines.
President and CEO
Amit Gupta is co-founder, President & CEO of Solido Design Automation Inc. In 1999, he co-founded Analog Design Automation Inc. (ADA), a startup for semiconductor design software. Over the next five years, as President & CEO and VP Marketing and Business Development, he helped the company grow through periods of target market identification, initial prototype development, field trial successes, product commercialization and launch, sales generation with quarterly revenue growth and acquisition by Synopsys Inc. To fund this growth, he raised investment from venture capital and government sources.
Prior to becoming an entrepreneur, he was product manager for the wireless group at Nortel Networks and a hardware engineer for the RF Communications group at Harris Corporation. He graduated with degrees in both Electrical Engineering and Computer Science with great Distinction from the University of Saskatchewan. He was awarded the 2005 outstanding alumni award for significant accomplishments since graduation.
VP Customer Applications
Kris Breen joined Solido in 2005, on the day it was founded. Serving as Lead Designer, he assembled and managed a team of skilled engineers and was responsible for evolving Solido’s new technology into the company’s first commercial product. Collaborating closely with several major semiconductor companies, Breen worked to unite Solido’s technology with the needs of circuit designers and the market as a whole. As the product matured, Breen shifted his focus to helping drive the successful deployment of Solido’s products into the market.
Breen has an M.Sc. degree in Electrical and Computer Engineering from the University of Alberta. He also holds degrees in Electrical Engineering and Computer Science from the University of Saskatchewan, where he was awarded the Governor General of Canada’s Silver Medal in 2002. Breen is a co-author of “Variation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide”.
VP Technical Operations
Jeff manages Solido’s product line and leads Solido’s research, product development, and quality assurance teams. He is a hands-on technologist who is often found working in the trenches with Solido’s customers to co-design novel tools and algorithms that solve production circuit design and manufacturing problems.
Jeff started with Solido back in 2006 and spent much of his time on the road meeting with designers and bringing knowledge back to align Solido’s early products with customer needs. He has been deeply involved since the near beginning in setting product direction, designing Solido’s core technologies, and in building up Solido’s expert development team.
Prior to working at Solido, Jeff spent a decade working in custom software development and led over 100 custom software projects. He also taught University Computer Science courses, and consulted in a variety of software development areas.
Board of Directors
Jim Hogan has worked in the semiconductor design and manufacturing industry for more than 33 years, serving as a senior executive in electronic design automation, semiconductor intellectual property, semiconductor equipment, and fabrication companies. Jim currently serves as chairman at Solido Design Automation and as director at Scoperta, Nimbic and Tela Innovations.
Jim also has held a variety of executive and board positions at several companies, including director at Altos Design Automation, managing partner at Telos Venture Partners, senior VP of business development at Artisan Components, and senior VP of business development and the senior member of the office of chief technologist at Cadence. Jim holds a BA degree in mathematics, a BS degree in computer science and an MBA, all from San Jose State University.
Jim Derbyshire is a serial entrepreneur with 23 years of high tech board experience. Most recently, Jim served as Chairman and CEO of Veridae Systems (Vancouver, BC, Canada), an EDA company acquired in June 2011 by Tektronix. Previously, he was Chairman and CEO of SiGe Semiconductor (Ottawa, ON, Canada and Andover, MA, USA), acquired by Skyworks, and Director and CEO of Symbionics and its subsidiary companies (Cambridge, UK), one of which was an IP and software licensing company acquired by Cadence Design. During his career, Jim has been on the boards of companies in the USA, Canada, Hong Kong, New Zealand and the United Kingdom. He has also worked for, and raised large rounds from, venture capital organizations and built successful business partnerships with leading companies in the US, Asia and Europe.
Keith Mueller has over 28 years of experience in the EDA and semiconductor industries, most recently as president/CEO of Tuscany Design Automation (sold to Dassault Systémes December 2012). He previously held VP of worldwide sales and marketing positions at Apache Design Solutions (acquired by Ansys in 2011), Silicon Perspective Corporation (SPC, acquired by Cadence Design Systems in 2001), and Anagram, Inc. (sold to Avant! in 1996). He was in management and sales positions at Quickturn Design Systems through its IPO (now a Cadence company) and at start-up Silicon Compilers, Inc., (purchased by Mentor Graphics in 1991). He has been through 17 mergers and acquisitions in his career in EDA. Keith has also held marketing positions at Quantum Corporation and National Semiconductor, where he also started his career as an IC design engineer. Keith holds a BSEE degree from Purdue, a MBA degree from Santa Clara University, and has one patent.
Phil Anzarut is a partner in the Diversified Portfolio. He joined BDC Venture Capital in 2009. Mr. Anzarut is a former investment banker, having begun his career in corporate finance at HSBC Securities. He has also worked independently, providing financial advisory services to Canadian small-cap companies. In 2001, he joined TELUS Corporation as Director of Corporate Development / Mergers & Acquisitions, and spent the next seven years leading acquisitions and strategic divestitures on behalf of TELUS – both at the corporate level and for TELUS Ventures. Mr. Anzarut has also led acquisitions on behalf of CAE Inc. in Montréal. He is a member of the Board of Directors of TBayTel and holds the ICD.D designation from the Institute of Corporate Directors.
Mr. Anzarut holds a Bachelor’s degree in Microbiology and Immunology from McGill University and an MBA from the Schulich School of Business at York University.
Tyler Bradley has 9 years of experience in venture capital and corporate finance in start-up and growth stage companies. Prior to joining the Westcap team in 2007, Mr. Bradley was an Investment Analyst for a seed-stage investment fund from 2005 to 2007, where he was responsible for new investments and portfolio management. Between 2001 and 2005, Mr. Bradley worked in various corporate finance roles with start-up and growth-stage companies. Mr. Bradley received his Bachelor of Commerce from the University of Saskatchewan and is a Chartered Financial Analyst (CFA) candidate. Mr. Bradley is an active member and Director for the Saskatchewan Young Professionals & Entrepreneurs.
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