Advisory Board

Patrick Drennan

Patrick Drennan was formerly Chief Technology Officer of Solido Design Automation Inc. Prior to joining Solido, Patrick was a Distinguished Member of the Technical Staff at Freescale Semiconductor (formerly Motorola, Inc.), where he was employed for over 14 years.

Patrick was one of the creators of the backwards propagation of variance (BPV) method for statistical characterization. This model guarantees consistency between simulation and silicon measurement and it is valid for all biases and geometries, which are significant attributes for design. His mismatch (local variation) model earned the Best Regular paper at the 2002 IEEE Custom Integrated Circuit Conference. He was the first to describe the impact of shallow trench isolation (STI) and well proximity effect (WPE) on design, demonstrating that the WPE produces a graded channel MOSFET. More importantly, he showed the catastrophic impact these unforeseen phenomena can have on circuit design. For this work, he received the Best Invited Paper at the 2006 IEEE Custom Integrated Circuit Conference. Patrick has extensive experience in measurement, modeling, characterization, test structure generation and design application of systematic and stochastic semiconductor variations.

Patrick received the B.S. degree in microelectronic engineering and M.S. degree in electrical engineering from Rochester Institute of Technology in 1991 and 1993 and the Ph.D. degree in electrical engineering from Arizona State University in 1999.

Jim Rutt

Jim Rutt was formerly CEO of Network Solutions Inc., (acquired by VeriSign Inc., NASDAQ: VRSN) which administered domain name spaces on the Internet. He co-founded Business Research Corp., which developed online information products for the investment community. Rutt also was the co-founder of First Call and has served as CEO of Thomson Technology Services Group; and CTO of the Thomson Corporation (TSE: TOC) as well as, Chief Strategy Officer of VeriSign, Inc. Rutt received his bachelor’s degree in management from the Massachusetts Institute of Technology and is a vice chairman of the Santa Fe Institute. He was also a researcher in residence at the institute, where he studied the application of complexity science to financial markets, social simulations and artificial intelligence.

Pallab Chatterjee

Mr. Chatterjee is currently CTO of SiliconMap, LLC which was started in 2000. Prior to SiliconMap, Mr. Chatterjee served since 1985 as President/CTO of P&D Engineering Consultants, Inc an independent consulting firm specializing in Mixed Signal designs and CAD flows. Prior to being independent he held R&D positions at Philips and Telmos Corp.

In addition to his participation in SiliconMap, he is an editor with EDN Worldwide and Chip Design Trends/Extension Media. The editorial roles are supplemented by activities as an industry analyst to the investment community (both trading firms and the private investor/venture capital firms).

SiliconMap, LLC has partnered with over 25 EDA firms and 10 wafer foundries in the course of developing interoperability solutions. Mr. Chatterjee participates on the Technical Advisory board of several semiconductor, EDA and IT/Security companies. Additionally he holds or has held positions the Board of Directors of the UC Berkeley Eng Alumni Society, as the Founder/Conference Chair for the Magma User Group, the IC Section Chair for the Mentor User Group and on the organizing committee of the ISQED conference.

Mr. Chatterjee holds a BSEE from UC Berkeley, a MSEE from San Jose State and has taught graduate course work at San Jose State and with Silicon Valley Technical Institute. Mr. Chatterjee is also an author of technical books available from Springer Publications and Technology & Imagination Press.

"I've used Variation Designer to increase performance and parametric yield for both 45nm and 28nm designs. Solido Variation Designer sped up our variation analysis by about 5x versus just using Cadence tools." -Glenn Murphy, Qualcomm

"Variation Designer is extremely scalable and is able to handle the high-capacity requirements imposed by large circuits with thousands of active devices." -Electronics Talk

"The motivation for using Solido's technology is to ensure that designs are robust. Variation Designer reduces overdesign." -Mary Olsson, Gary Smith EDA

"Using Cadence Virtuoso with Solido enables a comprehensive suite of variation-aware custom IC design techniques that lead to higher quality designs in less time." -Cadence Connections

"The combination of using TSMC technology with Variation Designer results in higher parametric yields, better power, performance, area and improved designer efficiency for our customers."-Tom Quan, TSMC

"Variation Designer provides a way for chip designers to analyze, identify and fix the effects of process variations on their designs."-Gabe Moretti, EE Times

"The company that ranked the second most user interest at DAC 2010 was Solido which sells variation tools for custom design." -John Cooley, DeepChip

"We've been using Solido for 3 years to do our variation analysis and debug. We used Solido on an LDO test chip and found which variation effect was causing it to fail in silicon." -Anonymous User, DeepChip

"The most interesting tool I saw at DAC was Solido's toolset for variation analysis. The GUI and scripts can help designers do faster variation analysis." -Anonymous User, DeepChip

"We are pleased to add Solido to our AMS Reference Flow. Solido further improved our aggressive setup and runtime criteria by an additional 40%." -Kunihiko Tsuboi, STARC

"Solido and HSPICE together enable fast, accurate variation-aware design methods that can remove risks associated with traditional variation-aware design." -Synopsys

See a Video Demo

Solido and TSMC Webinar Presentation

GSEDA Analyst Report on Variation Analysis and Design

Cadence Virtuoso with Solido White Paper

Synopsys HSPICE with Solido White Paper