Testimonials

“Solido Variation Designer bolts into our Cadence Virtuoso Analog Design Environment (ADE) and Spectre. Solido sped up our analysis by about 5x versus just using Cadence tools. I’ve used Solido to increase performance and parametric yield for both 45nm and 28nm designs, as variations can also significantly impact performance above 28nm. Learning Solido was so simple even a caveman could do it. Many tools claim to be easy to use and well integrated into Cadence, but Variation Designer really was. I was able to find real design issues that have now been corrected in my last tape-out. I have been very impressed with Solido products and continue to use them for my analog/mixed-signal SerDes designs. I would give them an A.”- Glenn Murphy, Qualcomm

“As part of our commitment to offering a robust custom IC solution that fully addresses variation issues, TSMC conducted a rigorous evaluation of Solido Variation Designer prior to including it in our first AMS Reference Flow. The combination of using TSMC technology with Variation Designer results in higher parametric yields, better power, performance, area and improved designer efficiency for our customers.”- Tom Quan, TSMC

“Monte Carlo analysis is a 1980′s solution and is inadequate for analog and mixed-signal designers who are desiging products in applications built around systems-on-a-chip. Analog and custom designers are seeing the effects of the 90nm and 65nm process variations that are affecting yield loss, performance, power and die area. Designs are failing, which is complicating the detection of the transistor failures. The motivation for using Solido’s technology is to ensure that designs are robust. Solido’s tools reduce overdesign.”
- Mary Olsson, analyst, Gary Smith EDA

“New tools are becoming an increasingly important requirement in analog EDA, particularly process variation design tools that can prevent circuit failures and over-design in analog/mixed-signal and custom integrated circuits. I’m excited about the opportunity to work with Solido in advancing its development and dissemination of such tools.”
- James Hogan

“Amit Gupta (CEO) and Trent McConaghy (CSO) founded Solido circa 2005 to target an emerging market opportunity: addressing the analog and custom digital simulation effects due to process variability for complex system-on-chip (SoC) designs. Frankly, we were intrigued to mention Solido Design because of the confluence of analog design at the DFM (design-for-manufacturing) level. Individually, these are among the fastest growing segments in the EDA market, but a market opportunity that combines these attributes for design variability analysis caught our attention and merited additional commentary.”
- Erach Desai, Principal of Investment Research, America’s Growth Capital

“New tools and technologies in the analog market segment are essential to meet the ever-increasing demand for complex analog/mixed-signal designs. Solido Design has assembled a strong founding team with the experience required to bring its product suite to market.”
- Larry Lam, Director of Technology Seed Investments, BDC Venture Capital

“Resolving process variation issues is becoming an increasingly important challenge in nanometer transistor-level designs. Solutions that can scale to handle large inter-related design and process data, and are flexible enough to allow rapid adaptation to new challenges, are much needed and will help drive the development of robust, cost-effective nanometer designs.”
- Mary Olsson, analyst, Gary Smith EDA

“Three goals of all design teams are to avoid yield loss and over-design, improve design robustness, and maximize designer productivity. When design teams achieve these goals, semiconductor companies and consumers win because it reduces their costs and gets products to market faster. Solido has produced an elegant solution to address these key areas for transistor-level nanometer designs.”
- Resve Saleh, NSERC/PMC-Sierra Chair Professor of Electrical and Computer Engineering at University of British Columbia

“Our discussions with major Japanese semiconductor companies has validated that Solido is on the forefront of providing technology that addresses emerging challenges in transistor-level design. The combination of our sales, consulting and systems integration services with Solido’s technology will give Japanese customers an unparalleled solution for their analog/mixed-signal and custom digital and memory needs.”
- Tomio Okachi, President, Aisys Corporation

Solido Design was named on the EE Times list of top emerging startups. “The startups on the Silicon 60 list are the companies involved in semiconductor chips, memory, MEMS, EDA software, embedded applications, foundry manufacturing, semiconductor production equipment, electronics subsystems, packaging and materials that have made an impression on EE Times editors. They are emerging companies to watch — for a wide variety of reasons.”
- Peter Clarke, EE Times

Variation Designer is a finalist for EDN Magazine’s 18th Annual Innovation Award. “The annual EDN Innovation Awards honor outstanding engineering professionals and products. The Innovation of the Year award recognizes unique, state-of-the-art electronics products in several categories.”
- Staff, EDN Magazine

Variation Designer was recognized in EDN Magazine’s list of Hot 100 Products. “The list recognizes those products and technologies we chose from our print and Web pages that our editors believe generated heat in the electronics community – from analog IC to test-and-measurement devices.”
- Staff, EDN Magazine

“The Variation Designer solution provides a way for chip designers to analyze, identify and fix the effects of process variations on their designs. It provides automatic capabilities to analyze and identify process variation-related failure mechanisms, but cedes control to designers to use the information in combination with their experience and knowledge to fix those problems in an interactive manner. The new solution strengthens Solido’s global position as an industry leader in process variation solutions for transistor-level design. Variation Designer is the most recent version of Solido’s EDA (electronic design automation) tools, and was developed through intense and detailed interaction with major Solido customers.”
- Gabe Moretti, EE Times

“Prediction is always a risky business, but in the world of chip and system design, there are some new methodologies, tools, and challenges that are clearly going to impact design and verification. In 2007, Solido Design Automation introduced transistor-level statistical design technology that promises new functionality well beyond conventional Monte Carlo simulation.”
- Richard Goering, Editor, SCD Source

“Based on the innovative results produced with ADA and the experiences gained from their first entry into EDA, the company deserves close attention as they are poised to make a major difference in the transistor level design world.”
- Pallab Chatterjee, Chip Design Magazine

“Designers will increasingly use statistical variability analysis to maintain reasonable yields on analog and high-peformance digital circuits built on 65nm, and especially on 45nm and below.”
- Christopher Labrecque, HSPICE Marketing Manager, Synopsys Inc.