June 8, 2015, edited transcript
I’m a CAD director for Cypress Semiconductor. I will give a quick summary of the variation-aware techniques and things that we have done over the course of the last year at Cypress. It will be a very quick summary of where we are, what we have learned and what we are deploying in the corporation.
First of all, the company overview: Cypress is a very broad supplier. I don’t know if you guys are aware or not, but we have recently merged with Spansion. So literally my responsibility has doubled over the course of the last few months. So you can imagine what I’ve been doing, right? So, the number of products that we have is quite significant, it is very large. It varies from F-RAMs and S-RAMs all the way down to complex touchscreen solutions, wireless products, etc. So, a very broad portfolio. And at the heart of everything that we do, appears to be analog. Analog is what customers want. Analog is what customers demand. Analog is what customers are willing to pay for, more importantly.
Overall design overview: For Cypress’s new corporation, we have a thousand designers worldwide at this point in time. My responsibility literally doubled in terms of designers, number of design centers, whole bunch of cores, etc. And my primary function is design methodology. I am the liaison that enables our designers to put together comprehensive design methods, including the automation, and which results in the first pass yield quality silicon, etc. So my organization does half the work, and half the work is done by the design community worldwide.
So Cypress, years ago, has switched to an IP-based economy. What does that really mean? Since 2010 or so, we recognize that the world is going to change and we have steadily marched toward what we call an IP economy.
Chip equals IP plus wires. It’s that simple, right? And the faster you can assemble your chip, the faster you get it out the door, the more advantage you have in the marketplace.
At Cypress we typically have four types of IP products. They are 1) hard, 2) soft, 3) hardened, meaning products that have some component of analog and digital and they are combined into one, and 4) finally, the generator or compiled IP.
The big divide between those types of IP blocks is differentiated versus non-differentiated IP. Non-differentiated IP basically you can think of it as, it has to be there. It just has to work, right?
Everybody wants an ARM core everybody wants a PLL, you must have them, right? But the customer is not really willing to pay for it. The differentiated IP is something that customers are willing to write a check for. It’s something that makes you stand out against your competition. It’s something that adds value to the end customer.
The differentiating IP, as I’ve already mentioned earlier, is by far the analog and mixed-signal content. That’s what differentiates Cypress products in the marketplace.
When I talk to my designers and I look at our cycle times, we have seen the SOC integration time, and again, keep in mind that, Cypress is a very much a mixed-signal design company. It’s a big A, big D. A lot of times we have higher analog content than we do digital content.
When we take a look at the SOC cycle times, they are completely dominated by the IP times. Putting together a chip, a complex SOC is not that hard. It’s a quarter or less, of five to six guys. Making IP – it’s millions of dollars of investment. So making those guys go faster and be more productive is the name of the game.
So, I sit on the sidelines, and again don’t forget that I’m more of a digital kind of guy. So I look at my designers and what I see from the outside is a typical game of Whack-A-Mole. The guys working, he’s working hard, his concentration is unwavering, but we’re not getting to the goal line. You keep getting told it’s only next week, maybe the week after. Two weeks go by, still same old schedule, next week for sure. And at some point, you have to step back and ask yourself, are we doing the wrong thing here? We’re driving a square peg into a round hole. Something was fundamentally wrong.
So about a year ago, Amit (Gupta) and I engaged, we started to learn a little bit more about the capabilities they (Solido) were offering. And don’t get me wrong, at Cypress we had a very complex set of DOEs that we would apply on our products and our analog designs, but it varied. It varied based on the designer experience, it varied on the continent you’re on, the language they speak, etc. So a more uniform, more common method of communicating and solving the problem was required.
And that’s why I titled that section “Moving with a purpose.” It’s significantly different from the old types of designs that we used to do. You would simply run, shotgun approach hoping the chip picked the right architecture, you’d done the proper verification and hoping that your yield and your circuits are going to work in the final environment.
What Solido was able to do for us is, allowed us to dynamically derive the corners that truly dominate your analog design. With that, our cycle times have tremendously shrunk, our quality of results has definitely reached our internal goals for 4-sigma and we have seen tremendous improvement in the overall quality of our design.
This slide talks about one of the weird architectures that we have in the company. It’s called a P-SOC, programmable system-on-a-chip. And even the title itself is kind like of an oxymoron. “Universal Analog Block” – it doesn’t make any sense. What’s universal about the analog design? Usually it’s, it’s very specific and tailored to the customer design. So P-SOC, you can think of the block basically as a combination of analog multiplexers, whole bunch of op-amps, variable capacitors that you can program to a certain function.
From this particular case study we have seen that the number of simulations that we have to do went from at least 10,000 simulations – that’s the best case scenario – to something like 1,000 simulations, a tremendous improvement in cycle time.
Overall, if you take a look at the numbers – on average we have reduced our cycle time, or our cost, by 20 man-weeks. The training and the learning for designers was not that difficult, it was roughly about 3 days per designer to ramp up to the new technology, the new capability, and we have literally done this in parallel as they were working toward the next design.
So if you think about, what have we lost by trying to deploy it? Literally, nothing.
The acceleration and the improvement definitely paid for itself first time out of the gate. On the average, we were saving something like 2.7 man-weeks on the architectural selection, 0.3 man-weeks on the rework and-2.4 man weeks for the reduced iterations.
On the silicon spins, Cypress follows a very rigorous process and root cause corrective action, so we have a very substantial amount of data. How often do we break analog products? How often do we break analog chips? And that turned out to be about 1.6 per year that we can actually prevent with the proper variation-aware design techniques.
And finally, the overall ROI for the company was 5.4 for one year and 8.6 with a 5-year ROI. So to this date we have had 2 active designs, 2 active analog circuits that we have actually taped out one in Q1. The second one’s taping out this quarter and we’re looking forward to getting the results back and finding out how well we’ve done. Thank you.
Panelist Questions & Answers
Question: In terms of deployment methodology, when deploying these tools into your organizations how have you done that? Have you used a particular method or what have your experiences been?
Cypress has a very formal process of adopting new tools. It starts with a complete market place evaluation decision whether we’re going to build or go ahead and buy, followed by the architectural documents, functional documents, final implementation, pilot process, the training, and the full deployment.
So it’s a long process, as you probably know. But once we do it – once we do it right – we never come back and have to redo it.
So, by following that process, with the full market analysis, we picked Solido as the solution of choice at Cypress Semiconductor and we decided to roll it out. We are past PR4, meaning our pilot project, and we are in the process of going to our PR5, which is the final full deployment. And I’m looking to have the complete PR5 milestone, which is 80 percent of the audience has been trained and using the tool, by the end of this quarter. So we’re within an inch of being fully done and deployed.
Question: When is it important to deploy variation-aware design methodology? Is it at specific node, or is it a specific power? What’s the compelling event?
For us it was 130 nm. Skyscraper size.
We found that the architecture, the problem that you are trying to solve for your end customer to drive the variation design requirement, in our case, it was a little bit different. We were not doing design for 6-sigma for high reliability. We were trying to optimize the cycle time for our designers.
We found that it definitely fits the bill. It does cut down the cycle time, therefore we went for it. So it’s a slightly different problem, driven by the architecture or application that you were trying to deploy.
Question: Jeff and Sifuei commented a little on usability. I was curious from the other panelists’ point of view, what were your thoughts on that?
Actually, I have a great story. So we have one designer that shall remain nameless. But he is one of the most senior analog designers in the company. He’s absolutely been an amazing asset on this program.
Usually if you ask him how you would like to change something, his answer is, “I don’t like it.”
So we had to go back and forth on the initial deployment, but literally, as we went through the initial phases of the evaluation, and he was engaged for about 2 weeks, we turned the licenses off because the evaluation was done.
I got a phone call back and he said “when can I have it back?”
And that spoke volumes to me. This was a very experienced designer, been using his DOE tool kit for years, and he has found added value in the proposition that Solido delivers. So it was a big testament.