June 8, 2015, Full Video Transcript & Slides Below
I’m Sifuei Ku. I work for Microsemi in the SOC division which is the old Actel. Let me just dive directly into what we’re going to discuss today. We’ll talk about the variation designers and our challenges in design. We have a lot of variation in models from foundries. That’s our experience with the foundry we’ve been using for 20 years – and they tend to have not very solid models.
Since we are designing FPGAs, we tend to also push the devices to the limit. We notice that we are actually using the devices a lot of times outside the well-categorized regions, so we want to make sure we are doing it correctly.
And then, we do have many repeater circuits that are especially sensitive to mismatches. For example, level shifters, sens amps and memories. We also need to have high confidence to make sure that the statistical variation doesn’t kill our circuit. And it’s a small world, as we are actually, are currently are working with Cypress using their SONOS technology. So, it’s very interesting.
What is the solution that we are looking for? We want to supplement our traditional PVT and Monte Carlo with high-sigma Monte Carlo.
And I was asked compared to how our previous software was, how does this work?
And to tell you the truth, we do not have any solution before. So, essentially we are going from zero to one, here.
So the evaluation process – the criteria was to make sure that, of course, the first thing was that the software needed to be able to detect issues. That’s the most important thing.
And since we are in the middle of the execution phase right now we’re at 28 nanometers technology. So we’ve designed this new design methodology. So it has to be easy to use, for both the CAD people to set it up and also for the designers that use it.
And also, one important thing is it actually has to fit our budget, or else my VP won’t sign-off on it.
So, why (Solido) Variation Designer? Why do we like the tools?
Actually, during the eval cycle it did catch several issues. So I guess we stacked the deck a little bit.
We had a chip that came back, it was last year, and we did have an issue in the pulse generator, in the ENVM, in the nonvolatile memory section; the designer after a while had figured out what the problem was.
However, we did the evaluation and we sent the exact circuit to Solido and their software caught it right away. So it actually zeroed into the issue that we believe the problem was.
And interesting also is that, if I remember correctly, we engaged the evaluation on Thursday, the CAD people got it up and running on Friday. And then the designer actually played with it on the weekend and actually on the designer’s first design, a level shifter, he found the issues on the weekend.
So, it was pretty good. We knew that the tool was actually doing what it was supposed to do.
The tool is also it’s very easy to use which is actually really important for designers, because we had been looking at other tools and a lot of tools out there are difficult to use.
Actually, I must pat Amit (Gupta) on the shoulder, I talked to Solido about 15 years ago. And I was in the conference room and the tool looked pretty raw then. It was hard to use, I believe, but I guess they’ve done a lot since then and it actually does show in the tools.
So that’s one of the biggest things. The designer really said this is really easy to use. And as I mentioned, the basic setup was done within days, in a day actually, including integration into our Cadence environment now.
We use Cadence Virtuoso and Composer. And the designer was up and running in days.
And the run time is reasonable as advertised and the work flow is quite efficient – our previous speakers had alluded to this. So, essentially you run fast simulations and then you drill down to specific corners that give you issues.
We used to do what we call the “British Museum Algorithm.” You walk everywhere. And if you don’t walk to right place, you miss something. Solido’s tool enables us to zero into the potential issues a lot faster.
And lastly, it’s fun to also say, we get tremendous AE support. The first day, when we tried to bring it up, apparently we had a looping model, that included itself. So it was causing a problem with the software. We gave them a test case and within hours the AE and the developer found the problems and actually fixed that for us. That was pretty good.
How about speed? So, for PVT we are actually seeing an average of about 1.7x reduction in the runtime. So actually just narrows down the problems about 1.7x.
And from the high-sigma standpoint, as I mentioned before right, we could never have run it before because it would have take billions of simulations and we couldn’t do that. So I talked to designers and they said that most of the circuits actually converged between 500 and 1000 simulations. I think that’s pretty comparable to what other speakers have said here.
And I know Solido has said that usually it will take about 3000-4000 simulations. But I think that’s conservative. Usually, between 500 to 1000 simulations, you see the graph is converging.
And lastly, we got a pretty good deal from a budget standpoint.
Another thing, and this is quite recent. We engaged with Solido on the Hierarchical Monte Carlo, and actually we ended up buying the tools after like 2 weeks of evaluations. We evaluated it on the full memory array we have.
Solido was able to construct this memory – this 15.6 million cell array – with all the bit lines and sense amps. And actually, what we do is that we run the Monte Carlo for our chip to 3 sigma, the sense amp is to 5.1 sigma and the bit cells to 6.2 sigma. We have a design team in Pennsylvania. They did this and they gave me this information.
And actually, I guess since this is high-sigma simulations, I guess I need to put in this 1.8 millionX. That’s what we actually see the savings because it’s supposed to be like 18 billion cycles which is not possible to run and we’ll be able to run that in about 8000 simulations, I’m sorry. From 18 billion simulations to about 8000 simulations. And we’re seeing a lot of improvement in the design.
So, the designers were really sold on this. That’s why we went back to our VP and asked for more money because actually we were outside our budget cycle by then but we ended up getting the tool so it was pretty good.
Question & Answer
Question: In terms of deployment methodology, when deploying these tools into your organizations how have you done that? Have you used a particular method or what have your experiences been?
We did see a problem in the silicon. We actually had a methodology review and we looked at it, and thought we should look at this kind of tool on the market. And we have less structure than Cypress, apparently. We knew Solido’s reputation in the marketplace. So we grabbed their tools and it worked right away and we just figured that we could use it.
Question: When is it important to deploy variation-aware design methodology? Is it at specific node, or is it a specific power? What’s the compelling event?
The problem that we found was actually on 65 nanometer nodes – we were surprised at that. And the current problem we’re working on is 28 nanometer which is going to be much, much more difficult. That was why we were worried that if we didn’t deploy variation-aware design methodology that we would really be in trouble.
Question: Jeff and Sifuei commented a little on usability. I was a curious from the other panelists point of view, what were your thoughts on that?
I think to expand Alfred’s point, that’s correct I mean they just launched it and a few minutes later they know where the critical stuff is, so that’s really key.
I think the same thing, I think all the senior designers in the world are like that, they don’t want the change, you tell them like, ‘Hey we’re putting in this new thing’, and they’re like, ‘No, I don’t want to know anything about that, just give me HSPICE’. And essentially it is HSPICE, with this thing running on top of it, and they’re really happy.
We have 10 copies and I know my VP asked me whether we should push the methodology outside our division to other divisions, and I said ‘well, looking at the license, I’m monitoring the license, it’s packed 24/7 at 10. It’s like, ‘No, we don’t want to push that out yet’. It’s going to get ugly when someone else steals our license, I don’t think our guys would like that very much, so it was interesting.