Recent News

April 30, 2012 NewElectronics – 100x faster Monte Carlo for memory design
April 24, 2012 EETimes – High-Sigma Monte Carlo for memory design
April 19, 2012 DeepChip – SPICE for memory design
March 5, 2012 SemiWiki – Survey of high-sigma Monte Carlo approaches
January 26, 2012 DeepChip – Custom IC Variation at CICC Report
January 5, 2012 Electronic Specifier – The same, but different
November 17, 2011 DeepChip – How to run Solido with 100′s BDA simulators
November 1, 2011 SemiWiki – Variation analysis in TSMC AMS Reference Flow
October 13, 2011 DeepChip – DAC 2011 Trip Report
October 5, 2011 ElektronikPraxis – Problems and solutions to variation design
September 26, 2011 SemiWiki – Solido & TSMC variation webinar for optimal yield in memory, analog, custom digital design
September 23, 2011 ElectronicsWeekly – Alternative to Monte Carlo for sub-micron design
September 18, 2011 SemiWiki – PVT and statistical design in nanometer process geometries
September 15, 2011 DeepChip – Gary Smith study on variation analysis and design for custom ICs
DeepChip – Cooley variation panel at DAC
August 30, 2011 DAC – Qualcomm usage of Solido High-Sigma Monte Carlo with HSPICE
NewElectronics – Issues and solutions for variation-aware custom IC design
August 29, 2011 SemiWiki – Semiconductor yield at 28nm HKMG
August 15, 2011 SemiWiki – DAC update for Solido
July 19, 2011 Video – Solido CSO on DAC 2011 announcements
July 18, 2011 SemiWiki – Variation analysis
July 12, 2011 Gary Smith EDA – Variation analysis and design for Custom ICs across SoC
June 1, 2011 EE Times – TSMC enhances 28nm reference flow with Solido update
May 26, 2011 DeepChip – Huawei engineer’s 65nm benchmark of Solido
April 29, 2011 EE Times – Survey points to variation-aware design as top custom IC focus
March 25, 2011 DeepChip – DATE 2011 Trip Report
February 8, 2011 EE Times – STARC adopts Solido variability tool
February 7, 2011 EE Journal – Is variation a real issue for designers?
February 1, 2011 DeepChip – Survey of 486 custom engineers on when variation bites you
January 5, 2011 SemiWiki – Variation-aware design survey results
December 7, 2010 DeepChip – Solido caught sneaky analog variation bug in our silicon
November 7, 2010 EETimes – Solido on EETimes Top 60 Startups List
October 8, 2010 DeepChip – Jim Hogan ranks variation-aware custom IC design vendors
September 2, 2010 DeepChip – Solido ranks top 2 in DAC 2010 report for most user interest
July 30, 2010 DeepChip – What Solido did to qualify for the new TSMC AMS Reference Flow
June 23, 2010 Chip Design – Variation in custom ICs: it’s not just a foundry issue
June 15, 2010 Chip Design – Solido Custom IC Design at DAC
Chip Design – Berkeley DA & Solido
June 11, 2010 DeepChip – Solido on Cooley DeepChip DAC Must See List
June 10, 2010 ChipDesign Mag – Corners Up, Margins Down
June 9, 2010 PRNewsWire – TSMC Selects Solido for TSMC AMS Reference Flow 1.0
June 8, 2010 TSMC – Solido in TSMC AMS Reference Flow 1.0
Silicon Valley Blog – TSMC Unveils First Ever AMS Reference Flow
EE Times – TSMC rolls two reference flows
June 1, 2010 Gary Smith EDA – Solido on Gary Smith’s What to See @ DAC 2010 List
Silicon Valley Blog – 47th Annual Design Automation Conference
May 27, 2010 DeepChip – User: Solido speeds Cadence Spectre variation design by 5X
May 21, 2010 EE Times Asia – Opinion: Custom IC design needs variation analysis
May 18, 2010 EE Times – Viewpoint: Current thoughts on custom IC design, Jim Hogan
April 12, 2010 EE Times – Solido on EE Times Top 60 Emerging Startups list
March 25, 2010 System-Level Design – Rounding Up Design Corners
February 8, 2010 TMCNet – Solido Opens Variation Designer Platform for Third Party Integration
January 28, 2010 TMCNet – Berkeley, Solido Collaborate to Enhance Nanometer IC Variation Analysis
January 27, 2010 EETimes – Berkeley, Solido claim faster IC variation analysis
TechBites – Berkeley and Solido team to provide IC variation solution
EDA Blog – Nanometer IC Variation Analysis Design Flow
January 26, 2010 AzoNanotechnology – Validated Flow for Rapid Reduction in Variation Risk in Nanometer Designs at Transistor Level
January 19, 2010 EDA Geek – Solido Design Automation Opens Up Variation Designer Platform
October 5, 2009 EETimes – Solido 60 Emerging Startups list
July 29, 2009 ChipDesign Magazine – Solido Design Overview
July 24, 2009 DeepChip – Must See List for DAC 2009
July 17, 2009 Canada.com – Solido receives $1.5M tax rebate
July 16, 2009 Saskatoon.com – Funding Boost for Local Business
Canada – Minister Blackburn delivers over $1.5 million in research and development investment tax credits to Solido Design Automation Inc
July 14, 2009 EETimes Analog – Analog/mixed signal design tools prominent at DAC 2009
June 26, 2009 Electronique – Solido Design Automation dote Variation Designer de l’analyse d’effet de proximité
June 24, 2009 EDN – Solido adds well-proximity estimation to Variation Designer
June 23, 2009 EETimes – Solido tool tackles sub-90 nm analog well proximity effect
March 5, 2009 EDN – Mitigating tapeout risk
February 17, 2009 EDN – Solido design attacks variations in transistor-level analog design
February 16, 2009 EETimes Analog – Process variation tool targets analog/mixed signal design loss
February 2, 2009 EETimes – Solido added to Silicon 60 Top Startups list
Hearst – Process variation tool is highly scalable
January 28, 2009 Electronics Talk – System solves process variation design problems
January 23, 2009 SOC Central – Solido Design Automation Launches xtensible Process Variation Solution
EETimes – Solido launches process variation solution
January 22, 2009 EDA Blog – Solido Variation Designer
December 1, 2008 EDN Europe – Mixed-signal-IC designers get help with nanometre processes
October 24, 2008 EETimes Analog – Process variation tool comes to Europe
October 23, 2008 Electronique – Solido Design Automation s’implante en Europe
September 2, 2008 SCD Source – Improving statistical design for analog/custom circuits
August 8, 2008 Elektronic Net – Statistische Variationen stellen kein Problem mehr dar
July 29, 2008 Elettronica – Eda, un settore ancora vitale
SCD Source – Solido Design’s statistical variation analysis is accurate and fast
June 20, 2008 ChipDesign Mag – Analog Designer Perspective on Analog at DAC 2008
June 11, 2008 ChipDesign Mag – DAC 2008 Trip Report
May 29, 2008 EDA Geek – DAC 2008 Features AMS Tutorial, Seminar from Solido Design
February 1, 2008 EDN – SolidoSTAT named finalist for EDN Innovation Award
EDN – SolidoSTAT named finalist for EDN Innovation Award
EETimes – Solido Design named on EE Times list of top emerging startups
January 2, 2008 SCD Source – Ten 2008 trends in system and chip design
December 14, 2007 EDN – SolidoSTAT named in EDN Hot 100 Products of 2007
September 17, 2007 Electronic Products – EDA tool targets nanometer designs
EDN – Startup Solido optimizes transistor-level statistical analysis
Electronics Talk – Software cuts parametric yield loss
Electronique – Solido Design Automation lance un outil de conception et de vérification statistique
September 14, 2007 EETimes – Solido makes analysis tool suite available to all
August 29, 2007 Electronique – Outils de conception statistiques : Solido lève 6,5 millions de dollars
August 28, 2007 EDN – EDA startup Solido closes on $9M in total venture funding
August 27, 2007 EETimes – EDA vendor Solido raises additional $6.5 million
March 1, 2007 ChipDesign Mag – Partnership Signals Japan’s A/MS Software Demand
February 14, 2007 EETimes Asia – Statistical tool avoids overdesign with excessive margins
EDN Asia – Solido announces new transistor-level statistical design and verification technology
February 12, 2007 ChipDesign Mag – Beyond Monte Carlo Analysis for Analog/Mixed-Signal, Custom Digital, and Memory Design
EETimes – Statistical tool targets analog, custom ICs
ChipDesign Mag – New Transistor-Level Statistical Design and Verification Technology
January 24, 2007 Electronics Talk – Virtual Subsidiary Targets Japanese Growth
EuroAsia Semiconductor – New partnership signals demand in Japanese market for analogue design software
November 8, 2006 Electronics Talk – Marcisz leads US sales offensive
September 13, 2006 Silicon India – Solido Raises $2.5M
September 12, 2006 EDN – EDA Startup Gets $2.5M in Private Investment
EETimes – Startup gets private funding, forms board of directors
July 17, 2006 EETimes – Tools tag 65 and 45nm ICs
July 11, 2006 ChipDesign Mag – Serial Entrepreneurs Not One-Hit Wonder
July 7, 2006 Private Equity Week Wire – Solido Design Automation
July 5, 2006 mCAD Cafe – DAC to Feature New Exhibitors
June 29, 2006 ChipDesign Mag – Max’s Chips and Dips
June 26, 2006 SOC Central – Entrepreneurs Launch Second EDA Company in Analog/Mixed-Signal Design Space
June 17, 2006 EETimes – Tool startups bet on autonomy
June 6, 2006 EETimes – Startup tackles transistor-level IC design

"Variation Designer is extremely scalable and is able to handle the high-capacity requirements imposed by large circuits with thousands of active devices." -Electronics Talk

"The motivation for using Solido's technology is to ensure that designs are robust. Variation Designer reduces overdesign." -Mary Olsson, Gary Smith EDA

"Using Cadence Virtuoso with Solido enables a comprehensive suite of variation-aware custom IC design techniques that lead to higher quality designs in less time." -Cadence Connections

"The combination of using TSMC technology with Variation Designer results in higher parametric yields, better power, performance, area and improved designer efficiency for our customers."-Tom Quan, TSMC

"Variation Designer provides a way for chip designers to analyze, identify and fix the effects of process variations on their designs."-Gabe Moretti, EE Times

"The company that ranked the second most user interest at DAC 2010 was Solido which sells variation tools for custom design." -John Cooley, DeepChip

"We've been using Solido for 3 years to do our variation analysis and debug. We used Solido on an LDO test chip and found which variation effect was causing it to fail in silicon." -Anonymous User, DeepChip

"The most interesting tool I saw at DAC was Solido's toolset for variation analysis. The GUI and scripts can help designers do faster variation analysis." -Anonymous User, DeepChip

"We are pleased to add Solido to our AMS Reference Flow. Solido further improved our aggressive setup and runtime criteria by an additional 40%." -Kunihiko Tsuboi, STARC

"Solido and HSPICE together enable fast, accurate variation-aware design methods that can remove risks associated with traditional variation-aware design." -Synopsys

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