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Solido Variation Designer is a fast, accurate, high capacity tool suite that improves design performance, parametric yield, and designer productivity by:
- Analyzing variation impact on design specifications
- Identifying transistor sensitivities to variation effects
- Fixing the design to meet specifications with closed-loop verfication
Variation Designer uses foundry models to address variation caused by process and environmental (PVT) corners, global and local random variation, and well proximity effects.
PVT Corner package speeds PVT corner design by up to 50x over traditional methods, allowing designers to comprehensively analyze PVT corner impact on design specifications, identify transistor sensitivities, and fix the design to meet specifications.
Statistical package speeds verification up to 10x for 3 sigma designs, and 100x-10,000x for >4 sigma designs compared to Monte Carlo analysis. It identifies transistor sensitivities to random variation and allows designers to fix the design to meet specifications.
Proximity package allows designers to determine guardband requirements to make designs robust to well proximity effects.
Variation Designer is integrated with existing custom IC design flows and is simulator agnostic, supporting Cadence Spectre, Synopsys HSPICE, Mentor Eldo and Berkeley Design Automation AFS simulators.
