Variation Designer Highlight Video

Outline

This 3 minute video shows Variation Designer being used to:

  1. Reduce the number of simulations required to uncover failures using DoE features of the PVT+ package
  2. Identify the cause of the failures with sensitivity analysis plots throughout the application
  3. Run exactly the right number of simulations to prove/disprove certain sigma goals with accuracy-aware analysis built into the Monte Carlo+ package
  4. Extract 3-sigma statistical corners which can then be used to analyze, identify and fix the design
  5. Verify design yield has been improved to 3-sigma
  6. Establish extreme tails of the distribution and to verify the design to 6-sigma with the High Sigma Monte Carlo+ package
  7. Save time and area by proactively designing for proximity effects with the Proximity+ package

For more information about Variation Designer and its constituent apps visit http://www.solidodesign.com/product/.

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"Variation Designer is extremely scalable and is able to handle the high-capacity requirements imposed by large circuits with thousands of active devices." -Electronics Talk

"The motivation for using Solido's technology is to ensure that designs are robust. Variation Designer reduces overdesign." -Mary Olsson, Gary Smith EDA

"Using Cadence Virtuoso with Solido enables a comprehensive suite of variation-aware custom IC design techniques that lead to higher quality designs in less time." -Cadence Connections

"The combination of using TSMC technology with Variation Designer results in higher parametric yields, better power, performance, area and improved designer efficiency for our customers."-Tom Quan, TSMC

"Variation Designer provides a way for chip designers to analyze, identify and fix the effects of process variations on their designs."-Gabe Moretti, EE Times

"The company that ranked the second most user interest at DAC 2010 was Solido which sells variation tools for custom design." -John Cooley, DeepChip

"We've been using Solido for 3 years to do our variation analysis and debug. We used Solido on an LDO test chip and found which variation effect was causing it to fail in silicon." -Anonymous User, DeepChip

"The most interesting tool I saw at DAC was Solido's toolset for variation analysis. The GUI and scripts can help designers do faster variation analysis." -Anonymous User, DeepChip

"We are pleased to add Solido to our AMS Reference Flow. Solido further improved our aggressive setup and runtime criteria by an additional 40%." -Kunihiko Tsuboi, STARC

"Solido and HSPICE together enable fast, accurate variation-aware design methods that can remove risks associated with traditional variation-aware design." -Synopsys

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