Webinar

High-efficiency PVT and Monte Carlo analysis in TSMC AMS Reference Flow for optimal yield in memory, analog and digital design

In a recent independent survey, variation-aware custom IC design was ranked the number one area requiring advancement over the next two years. The survey revealed:

  1. 53% of design groups missed deadlines or experienced respins due to variation issues
  2. Designers experienced an average 2 month delay due to variation issues
  3. Designers spent an average 22% of design time on variation issues

For further information, see the Gary Smith EDA analyst report on variation design.

Attendees of this webinar learned:

  1. Variation challenges in custom IC design
  2. Variation-aware solutions available in the TSMC AMS reference flow
  3. Methods to develop and verify designs over PVT corners in less time
  4. How to efficiently apply Monte Carlo techniques in design sign-off
  5. How Monte Carlo is really possible up to 6-sigma
  6. Customer case studies of the above methods

Solido customer case studies include:

  1. NVIDIA for memory, standard cell, analog/RF design
  2. Qualcomm for memory design
  3. Huawei-HiSilicon for analog design
  4. Qualcomm for I/O design
  5. Anonymous for analog/RF design

Presenters:

  1. Nigel Bleasdale, Director of Product Management, Solido Design Automation
  2. Jason Chen, Design Methodology and Service Marketing, TSMC

Audience: Circuit Designers, Design Managers, CAD Engineers

Download presentation (pdf)

"Variation Designer is extremely scalable and is able to handle the high-capacity requirements imposed by large circuits with thousands of active devices." -Electronics Talk

"The motivation for using Solido's technology is to ensure that designs are robust. Variation Designer reduces overdesign." -Mary Olsson, Gary Smith EDA

"Using Cadence Virtuoso with Solido enables a comprehensive suite of variation-aware custom IC design techniques that lead to higher quality designs in less time." -Cadence Connections

"The combination of using TSMC technology with Variation Designer results in higher parametric yields, better power, performance, area and improved designer efficiency for our customers."-Tom Quan, TSMC

"Variation Designer provides a way for chip designers to analyze, identify and fix the effects of process variations on their designs."-Gabe Moretti, EE Times

"The company that ranked the second most user interest at DAC 2010 was Solido which sells variation tools for custom design." -John Cooley, DeepChip

"We've been using Solido for 3 years to do our variation analysis and debug. We used Solido on an LDO test chip and found which variation effect was causing it to fail in silicon." -Anonymous User, DeepChip

"The most interesting tool I saw at DAC was Solido's toolset for variation analysis. The GUI and scripts can help designers do faster variation analysis." -Anonymous User, DeepChip

"We are pleased to add Solido to our AMS Reference Flow. Solido further improved our aggressive setup and runtime criteria by an additional 40%." -Kunihiko Tsuboi, STARC

"Solido and HSPICE together enable fast, accurate variation-aware design methods that can remove risks associated with traditional variation-aware design." -Synopsys

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