Cadence Virtuoso with Solido for Variation-Aware Design White Paper

Process variation in custom semiconductor designs causes yield loss and re-spins, which in turn cause delays in delivering products to market as well as financial losses. To counter the effects of variation, foundries release models that describe variation for each manufacturing process. This model information is then used by designers to estimate the effects of variation during the design cycle, and to improve the design to make it robust to manufacturing variation effects. This is variation-aware custom IC design.

Addressing current generation process variation problems thoroughly is a complex, time-consuming, and expensive proposition. In particular, verifying designs with SPICE simulation across a comprehensive range of process, voltage, and temperature (PVT) corners and running exhaustive Monte Carlo simulations can take days and weeks. Moreover, when a variation problem appears in simulation, diagnosing and solving the problem can also take considerable time, which puts product to market deadlines at risk and increases costs. The alternative, not designing for variation, comes with even higher costs of re-spins and time-to-market delays.

Solido Design Automation has partnered with Cadence Design Systems through the Cadence Connections program to provide a Solido Variation Designer – Cadence® Virtuoso® Platform integrated solution. This paper discusses a collection of fast and accurate variation-aware custom IC design techniques that are possible using Cadence Virtuoso Analog Design Environment, Solido Variation Designer, and Cadence Virtuoso Multi-Mode Simulation (Spectre® Circuit Simulator, Accelerated Parallel Simulator, UltraSim Full-Chip Simulator) together.

Content Overview:

1. Variation-Aware Custom IC Design Challenges
2. Variation-Aware Custom IC Design Techniques
2.1 Maximize variation-aware simulation throughput
2.2 Efficiently verify across the whole PVT space
2.3 Precisely analyze mismatch effects
2.4 Quickly verify against random variation
2.5 Verify random variation beyond 3-sigma
2.6 Prepare the design for layout
2.7 Effectively verify post-layout
3. Summary

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