Synopsys HSPICE with Solido for Variation-Aware Design White Paper
Variation is affecting custom IC designs increasingly as process technologies shrink, and designing for variation is now a required step in successfully delivering a product. To enable design for variation, foundries release models that describe the variation. These models can provide excellent insight as to how variation will affect a design. The design challenge is to make the most effective use of the foundry models provided to measure the effects of variation, to optimize the design for variation, and to do so within the tight product design schedule. Ineffective variation-aware design adds schedule risk, product yield risk, and product quality risk.
Solido Design Automation and Synopsys have partnered to provide a comprehensive, fast, and accurate variation-aware custom IC design solution. Together, they reduce variation-aware design risks to reliably deliver competitive, profitable products on schedule. This paper discusses methods for eliminating schedule, product yield, and product quality risks that are enabled using Solido Variation Designer and Synopsys HSPICE.
Content Overview:
1. Variation-Aware Design Risks
2. HSPICE and Variation Designer Integration
3. Reducing Schedule Risk
- Completing PVT and Monte Carlo Analyses Reliably
- Increasing PVT and Monte Carlo Speed with a Scalable Parallel Simulation Engine
- Designing for Variation From the Start
- Avoiding Proximity Problems
4. Reducing Product Yield Risk
- Increasing PVT Corner Coverage
- Improving Monte Carlo Accuracy
- Verifying Post-layout with PVT Corners and Monte Carlo
5. Reducing Product Quality Risk
- Tightening Design Margins with Improved Variation-Aware Precision
- Identifying Precise Causes of Variation Problems
- Running Variation-Aware Geometry Sweeps
- Reducing Area and Power
- Reducing Proximity Guard Band Area
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