Proximity+ Package

The Variation Designer Proximity+ Package enables designers to avoid heuristics-based conservative guard-banding and multiple iterations between circuit and layout. Instead, designers are able to proactively address well proximity effects during the circuit design stage.

Layout dependent proximity effects have an increasing impact on variation in transistor characteristics at deep nanometer technology nodes. Accounting for these effects with time consuming post-layout simulations can result in tapeout delays and this is further exacerbated by schematic-to-layout iterations. Using heuristics based guesses to guard-band for these effects can lead to area penalties which can be unacceptable in area critical designs.

Traditionally, there have been two ways to deal with proximity effects. In one, because it is not known at the circuit design stage which devices are sensitive to the effects, the designer uses heuristics to conservatively guard-band devices. This results in area penalties. In the other approach, the circuit designer obtains post-layout extracted netlists and simulates to determine if there are any proximity effect-related issues. This is an iterative process and results in design time penalties.

Variation Designer and the Proximity package provides a pre-layout analysis capability that allows designers to identify and fix devices that are sensitive to proximity effects. It increases design efficiency by reducing the need for iterative post-layout simulations for sensitive devices. It results in area savings by avoiding application of default guidelines.

The Solve Well Proximity application uses foundry-provided well proximity parameters that are included in the SPICE model files but are not normally used due to the lack of appropriate tools at the circuit design stage.

This application is used by a designer during the circuit design stage to proactively account for well proximity effects. The designer can determine which devices are sensitive to proximity effects and by how much, and can obtain the appropriate proximity parameter values and minimum well distances. These values are back-annotated into the schematic and are then used by the layout engineer, reducing the silicon area occupied by excessive guard-banding and eliminating the time consumed by iterative post-layout simulations.