Variation Designer

Download Variation Designer Datasheet

Process variation in custom semiconductor designs causes yield loss and re-spins, which in turn cause delays in delivering products to market and financial losses. To counter the effects of variation, foundries release models that describe variation for each manufacturing process. This model information is then used by designers to estimate the effects of variation during the design cycle, and to improve the design to make it robust to manufacturing variation effects. This is variation-aware custom IC design.

The Variation Designer platform is the world’s most advanced solution to variation challenges affecting analog, mixed-signal, and custom digital designs. It includes a comprehensive suite of variation-aware design apps that can be used pre- and post-layout to address PVT, statistical, and proximity variation. Variation Designer integrates seamlessly with leading simulators, design environments, and foundry models to provide 20-100% better area, power, performance, and yield, as well as a reduction in variation design time of over 50%.

Variation Designer is used across the transistor level design cycle – from PVT corner simulations to statistical analysis – to determine mismatch effects or yield. The platform is also useful for post-layout verification and, if required, for silicon debug. Intuitive to learn and easy to use, this interactive tool puts the designer in control. Variation Designer provides a systematic and consistent variation design flow for various transistor level design types (analog/RF, IO, memory or standard cell digital) that is integrated with various simulator and design environments, providing a consistent interface to designers irrespective of their specific tool environments.

Solido SPICE-based variation design tools span the design cycle

Variation Designer has been deployed for various flows such as Cadence® Virtuoso® Analog Design Environment (ADE) with Spectre Circuit Simulator, Virtuoso ADE or netlist with Synopsys’ HSPICE® Circuit Simulator, Virtuoso ADE and netlist with Berkeley Design Automation’s Analog FastSPICE simulator.

Solido Solution Architecture