Variation Designer 4
The world’s best technology for variation-aware design of memory, analog/RF, and standard cells.
- Sets the standard for semiconductor variation-aware design
- Full design coverage in orders-of-magnitude fewer simulations with accuracy of brute force techniques
- Improves design performance, power, area, and yield
- Perfect tool for solving real production design challenges in memory, analog/RF, and standard cell design
- Used by 1000+ designers across 40+ major semiconductor companies
- Proven in customer and production environments
- Compatible with any EDA design flow
- Powered by machine learning technologies
Full Chip Memory and Cell Level Statistical Verification
Memory designs are notoriously hard to verify against statistical process variation due to the need to verify components to high-sigma, and to verify components within critical paths to multiple high-sigma targets simultaneously. Inaccuracy leads to uncertainty, and when faced with uncertainty, designers, who must make chips that work, do things like add redundancy, increase minimum supply voltages, slow down memories, and increase feature sizes to make them more resilient to variation. This is bad – it results in memory designs that perform worse and are more expensive to manufacture. In the case where the memory actually fails, it can be even worse, as respins are really expensive.
Solido Variation Designer includes the two most advanced and industry-proven technologies for solving these problems:
- High-Sigma Monte Carlo: Delivers perfect Monte Carlo and SPICE accuracy all the way to 7-sigma in minutes to hours. It handles binary outputs, supports huge capacities, has great variation debugging capabilities, is easy to learn and use, is reliable, and is verifiable.
- Hierarchical Monte Carlo: Statistically reconstructs the entire on-chip memory with perfect frequencies and SPICE accuracy, while simulating just the memory slice or critical path. And it has all of the other powerful niceties of High-Sigma Monte Carlo mentioned above.
- PVTMC Verifier: The best way to get unprecedented coverage across all PVT conditions, to high sigma, in all conditions. Best used for bit cell or sense amp studies, in conjunction with High Sigma Monte Carlo to verify to high sigma.
In short, Solido’s memory solutions give the right answer so that memories do not have to be over-margined for uncertainty. This produces more competitive memory IP that is cheaper to produce.
And with hundreds of memory designers using Solido’s memory solution for every product cycle for many years now, it is also the most production proven and most trusted solution in the world.
Statistical & PVT Verification and Debug
Solido’s analog/RF solutions give unprecedented insight into variation effects in just hundreds of simulations, so designers do not have to over-margin to account for variation uncertainty.
Analog/RF designs often suffer from inadequate variation coverage. First, PVT and statistical variation are usually under-considered. If simulation were free, we would simply run Monte Carlo analysis with 5K samples at every PVT condition – this would give us near perfect information. The one thing that would still be wrong is that foundry process corners do not bound analog and RF designs. For example, a slow-slow global (SSG) corner typically bounds 3-sigma global variation for delays for nmos and pmos devices, and has nothing to do with 3-sigma global process variation for gain on an opamp. So what we really should be doing, if simulation were free, is running global and local statistical variation with 5K samples, and doing it at every PVT corner. That would actually be perfect information for 3-sigma designs, but it would take way too long to run. When targeting 4-sigma, as we often do for automotive parts or medical devices, it becomes even more impossible to do the right thing, as we need to run on the order of 1M samples to verify to 4-sigma correctly.
Solido Variation Designer delivers full statistical and PVT coverage with design-specific and output-specific analog corners in just hundreds of simulations. They also accelerate variation debugging by revealing the sources of variation problems and by identifying design solutions. Here are some of the key analog / RF tools in the suite:
- PVTMC Verifier: Comprehensive statistical process verification across all PVT conditions in just 100s-1000s of simulations.
- Fast PVT: Provides full PVT coverage while only simulating a small subset of the corners. This is accomplished using an advanced machine learning algorithm that predicts output values for non-worst case PVTs and ensures that all potentially worst-case PVTs are simulated in SPICE.
- Fast Monte Carlo: Delivers better Monte Carlo accuracy with fewer simulations, and enables fast, well-targeted variation debugging. Plus, it can be used to create correct design-specific and output-specific analog statistical corners with both global and local variation.
- Statistical PVT: Covers the full PVT and statistical space efficiently in a single job. It starts by creating correct analog statistical corners, then covers the full statistical PVT space efficiently using a machine learning approach. The result is unprecedented accuracy and coverage in just hundreds of simulations.
Solido’s analog/RF tools, combined with methodology collaboration, outstanding user training, and support, consistently advance the way our customers look at variation for analog/RF designs. The end result is that our customers produce better chips with less over-design and in less time.
Statistical Verification and Sizing of Cell Libraries
At advanced processes and low voltage, statistical variation has a big impact on standard cell delays and transition times – distributions skew from well-behaved Gaussian to extremely long tails. It is simply not sufficient to add a bit of margin for statistical variation or to use sloppy, inaccurate Monte Carlo techniques. To make libraries that are suited for low power design, it is essential to verify them thoroughly, and often to high-sigma, as many instances are placed on chips and they all need to work for a chip to work. Given the massive scope of standard cell verification and already exhausted CPUs and tool licenses, it is simply not feasible to do proper brute-force statistical analysis and meet production schedules.
Solido has effective and production-proven technology for accelerating statistical verification and tuning of standard cells. We have an excellent batch interface and built-in error recovery mechanisms for powering through large workloads of standard cell analysis automatically. Just batch it up and let it go – it’s way faster, more accurate, and more resilient than traditional methods. The main technologies that our standard cell customers use for heavy lifting are:
- Fast Monte Carlo: Perfect for running big batches of standard cells out to 3-sigma quickly, accurately, and reliably.
- High-Sigma Monte Carlo: The world’s most used, most trusted tool for measuring standard cells out to high sigma. It is fast, accurate, and works with binary measurements.
- PVTMC Verifier: Achieve unprecedented coverage across all PVT conditions in just one run, up to high sigma when combined with High Sigma Monte Carlo. Verify that all operating conditions required by your customers is covered in only 100s – 1000s of simulations.
Plus, we have an outstanding team of hackers who can help create scripts to do exactly what you want and to produce summaries and reports that contain all of the information you are looking for.
Variation Designer Standard is the suite of core variation-aware design capabilities required for verifying and debugging designs. These capabilities make it possible to perform variation-aware design with significantly greater accuracy and fewer simulations than traditional methods. They also open up a much greater level of insight into how variation affects designs. This information allows designers to make the best possible design tradeoffs, avoid catastrophic problems & failures, and quickly deliver more competitive designs than ever before.
Unprecedented coverage and speed for PVT and Monte Carlo verification
2-50X faster verification across environment and process corners
AdvancedVariation Designer Advanced is the ultimate variation-aware design package. It includes Hierarchical Monte Carlo, a remarkable technology for statistically verifying full chip memories within production timelines. With Variation Designer Advanced, designers can verify their designs in ways that have never before been possible. As one customer put it, Variation Designer Advanced “answers literally thousands of questions that we could only guess at previously”.
Hierarchical Monte Carlo