Variation Designer 4

The world’s best technology for variation-aware design of memory, analog/RF, and standard cells.

Variation Designer sets the standard for semiconductor variation-aware circuit design. Delivering the world’s most advanced variation analysis technologies, it’s the perfect tool for solving real production design challenges in memory, analog/RF, and standard cell design. That’s why 1000+ designers across 35+ major semiconductor companies trust Variation Designer to verify their designs.

Memory

Memory

Full Chip Memory and Cell Level Statistical Verification

Memory designs are notoriously hard to verify against statistical process variation due to the need to verify components to high-sigma, and to verify components within critical paths to multiple high-sigma targets simultaneously. Inaccuracy leads to uncertainty, and when faced with uncertainty, designers, who must make chips that work, do things like add redundancy, increase minimum supply voltages, slow down memories, and increase feature sizes to make them more resilient to variation. This is bad – it results in memory designs that perform worse and are more expensive to manufacture. In the case where the memory actually fails, it can be even worse, as respins are really expensive.

Solido Variation Designer includes the two most advanced and industry-proven technologies for solving these problems:

  • High-Sigma Monte Carlo: Delivers perfect Monte Carlo and SPICE accuracy all the way to 7-sigma in minutes to hours. It handles binary outputs, supports huge capacities, has great variation debugging capabilities, is easy to learn and use, is reliable, and is verifiable.
  • Hierarchical Monte Carlo: Statistically reconstructs the entire on-chip memory with perfect frequencies and SPICE accuracy, while simulating just the memory slice or critical path. And it has all of the other powerful niceties of High-Sigma Monte Carlo mentioned above.

In short, Solido’s memory solutions give the right answer so that memories do not have to be over-margined for uncertainty. This produces more competitive memory IP that is cheaper to produce.

And with hundreds of memory designers using Solido’s memory solution for every product cycle for many years now, it is also the most production proven and most trusted solution in the world.

Analog R/F

Analog/RF

Statistical & PVT Verification and Debug

Solido’s analog/RF solutions give unprecedented insight into variation effects in just hundreds of simulations, so designers do not have to over-margin to account for variation uncertainty.

Analog/RF designs often suffer from inadequate variation coverage. First, PVT and statistical variation are usually under-considered. If simulation were free, we would simply run Monte Carlo analysis with 5K samples at every PVT condition – this would give us near perfect information. The one thing that would still be wrong is that foundry process corners do not bound analog and RF designs. For example, a slow-slow global (SSG) corner typically bounds 3-sigma global variation for delays for nmos and pmos devices, and has nothing to do with 3-sigma global process variation for gain on an opamp. So what we really should be doing, if simulation were free, is running global and local statistical variation with 5K samples, and doing it at every PVT corner. That would actually be perfect information for 3-sigma designs, but it would take way too long to run. When targeting 4-sigma, as we often do for automotive parts or medical devices, it becomes even more impossible to do the right thing, as we need to run on the order of 1M samples to verify to 4-sigma correctly.

Solido Variation Designer delivers full statistical and PVT coverage with design-specific and output-specific analog corners in just hundreds of simulations. They also accelerate variation debugging by revealing the sources of variation problems and by identifying design solutions. Here are some of the key analog / RF tools in the suite:

  • Fast PVT: Provides full PVT coverage while only simulating a small subset of the corners. This is accomplished using an advanced machine learning algorithm that predicts output values for non-worst case PVTs and ensures that all potentially worst-case PVTs are simulated in SPICE.
  • Fast Monte Carlo: Delivers better Monte Carlo accuracy with fewer simulations, and enables fast, well-targeted variation debugging. Plus, it can be used to create correct design-specific and output-specific analog statistical corners with both global and local variation.
  • Statistical PVT: Covers the full PVT and statistical space efficiently in a single job. It starts by creating correct analog statistical corners, then covers the full statistical PVT space efficiently using a machine learning approach. The result is unprecedented accuracy and coverage in just hundreds of simulations.

Solido’s analog/RF tools, combined with methodology collaboration, outstanding user training, and support, consistently advance the way our customers look at variation for analog/RF designs. The end result is that our customers produce better chips with less over-design and in less time.

Standard Cell

Standard Cell

Statistical Verification and Sizing of Cell Libraries

At advanced processes and low voltage, statistical variation has a big impact on standard cell delays and transition times – distributions skew from well-behaved Gaussian to extremely long tails. It is simply not sufficient to add a bit of margin for statistical variation or to use sloppy, inaccurate Monte Carlo techniques. To make libraries that are suited for low power design, it is essential to verify them thoroughly, and often to high-sigma, as many instances are placed on chips and they all need to work for a chip to work. Given the massive scope of standard cell verification and already exhausted CPUs and tool licenses, it is simply not feasible to do proper brute-force statistical analysis and meet production schedules.

Solido has effective and production-proven technology for accelerating statistical verification and tuning of standard cells. We have an excellent batch interface and built-in error recovery mechanisms for powering through large workloads of standard cell analysis automatically. Just batch it up and let it go – it’s way faster, more accurate, and more resilient than traditional methods. The main technologies that our standard cell customers use for heavy lifting are:

  • Fast Monte Carlo: Perfect for running big batches of standard cells out to 3-sigma quickly, accurately, and reliably.
  • High-Sigma Monte Carlo: The world’s most used, most trusted tool for measuring standard cells out to high sigma. It is fast, accurate, and works with binary measurements.

Plus, we have an outstanding team of hackers who can help create scripts to do exactly what you want and to produce summaries and reports that contain all of the information you are looking for.

Customer Cases

Solido’s customers consistently see high value from our products, methodology collaboration, training, and support. This is a collection of some of the great things our customers have said about us over the years, directly from the source – our customers themselves.

NVIDIA

NVIDIA

NVIDIA Corporation is the worldwide leader in graphics processors and media and communications devices.

Case Study: Solido Variation Designer for memory, standard cell, RF design

Broadcom

Broadcom

Broadcom is a global leader and innovator in semiconductor solutions for wired and wireless communications.

Case Study: Solido Variation Designer for memory, std cell, custom digital and analog/RF design

Huawei

Huawei

Huawei is a leading global information and communications technology solutions provider.

Case Study: Solido Variation Designer for analog design

Cypress Perform

Cypress Semiconductor

Cypress delivers high-performance, high-quality solutions at the heart of today’s most advanced embedded systems, from automotive, industrial and networking platforms to highly interactive consumer and mobile devices.

Case Study: Solido Variation Designer for analog design

Microsemi

Microsemi

Microsemi Corporation offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets.

Case Study: Solido Variation Designer for analog and memory design

Applied Micro Circuits

Applied Micro Circuits

Applied Micro Circuits Corporation is a global leader in computing and connectivity solutions for next-generation cloud infrastructure and data centers.

Case Study: Solido Variation Designer for memory design

Taiwan Semiconductor Manufacturing Company

TSMC

TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry segment’s largest portfolio of process-proven libraries, IPs, design tools and reference flows

Case Study: Solido Variation Designer for memory, std cell design
Case Study: Solido Variation Designer for memory design
Case Study: Solido Variation Designer for analog/RF design
Webinar: Solido Variation Designer for memory, analog, custom digital design

GLOBALFOUNDRIES

GLOBALFOUNDRIES

GLOBALFOUNDRIES is the world’s first full-service semiconductor foundry with a truly global footprint.

Case Study: Solido Variation Designer for analog/RF design
Case Study: Solido Variation Designer for memory design

NSCore

NSCore

NSCore offers complete packages of licenses, design parameters, macro databases and foundry proven yield and reliability data of breakthrough NVM technology.

Case Study: Solido Variation Designer for memory design

Sidense

Sidense

Sidense Corp. provides very dense, highly reliable and secure non-volatile one-time programmable (OTP) Logic Non-Volatile Memory (LNVM) IP for use in standard-logic CMOS processes.

Case Study: Solido Variation Designer for memory design

KAIST

KAIST

KAIST is a public research university located in South Korea. KAIST was established by the Korean government with the help of American policymakers in 1971 as the nation’s first research oriented science and engineering institution.

Case Study: Solido Variation Designer for memory design

INVECAS

INVECAS

INVECAS is one of the leading producers of a wide variety of silicon-proven, high-speed IP solutions that are designed exclusively for GLOBALFOUNDRIES leading edge processes. These solutions deliver exemplary performance for today’s SoC’s.

Case Study: INVECAS Adopts Solido Variation Designer for Memory, Standard Cell, and Analog IP Design
Case Study: John Barth, DAC 2016

IBM

IBM

IBM manufactures and markets computer hardware, middleware and software and offers infrastructure, hosting and consulting services in areas ranging from mainframe computers to nanotechnology.

Case Study: Glen Wiedemeier, DAC 2016

ARM

ARM

ARM’s primary business is in the design of ARM processors (CPUs), although it also designs software development tools under the DS-5, RealView and Keil brands, as well as systems and platforms, system-on-a-chip (SoC) infrastructure and software.

Case Study: Azeez Bhavangarwala, DAC 2016

Qualcomm

Qualcomm Inc. is a semiconductor and telecommunications equipment company that is best known for its world-class mobile system on a chip (SoC) product brand, the Snapdragon, as well as innovative designs in a variety of other wireless telecommunication products and services.

Case Study: User says Solido speeds up Cadence Spectre variation design by 5X
Case Study: User verifies 6-sigma SRAM with Synopsys HSPICE and Solido

Deepchip User Reviews

DeepChip User Reviews

DeepChip.com is a 20 year old clearinghouse where semiconductor chip designers contribute data-intensive papers and articles of first-hand evaluations and production benchmarks of commercial EDA tools.

Case Study: Solido Variation Designer for memory design
Case Study: Solido Variation Designer for analog/RF design
Case Study: Solido Variation Designer for analog/RF design
Case Study: Solido Variation Designer for memory, std cell, analog/RF design
User Reviews: Design Automation Conference 2015
User Reviews: Design Automation Conference 2014
User Reviews: Design Automation Conference 2013
User Reviews: Design Automation Conference 2012
User Reviews: Design Automation Conference 2011
User Reviews: Design Automation Conference 2010
Cooley variation panel at DAC
Survey of 486 engineers on variation

Editions & Technologies

Standard

Variation Designer Standard is the suite of core variation-aware design capabilities required for verifying and debugging designs. These capabilities make it possible to perform variation-aware design with significantly greater accuracy and fewer simulations than traditional methods. They also open up a much greater level of insight into how variation affects designs. This information allows designers to make the best possible design tradeoffs, avoid catastrophic problems & failures, and quickly deliver more competitive designs than ever before.

Statistical PVT

Statistical PVT

Unprecedented coverage and speed for PVT and Monte Carlo verification

Fast PVT

Fast PVT

2-50X faster verification across environment and process corners

Fast Monte Carlo

Fast Monte Carlo

Fast and accurate 3σ design & verification using Monte Carlo

Interactive Environment

Interactive Environment

Interactive results visualization, fast design iteration, design history & versioning, netlist editor

Premium

Variation Designer Premium includes High-Sigma Monte Carlo, the world’s most trusted and production-proven high-sigma verification solution. Variation Designer Premium is the workhorse behind the industry’s most relied-upon variation design flows, from verifying replicated memory structures to verifying analog designs to be robust in today’s latest technologies.

Includes all capabilities in Standard edition, plus:

High Sigma Monte Carlo

High-Sigma Monte Carlo

Monte Carlo & SPICE accurate, verifiable high-sigma verification

Cell Optimizer

Cell Optimizer

Fast variation-aware cell-level optimization

Advanced

Variation Designer Advanced is the ultimate variation-aware design package. It includes Hierarchical Monte Carlo, a remarkable technology for statistically verifying full chip memories within production timelines. With Variation Designer Advanced, designers can verify their designs in ways that have never before been possible. As one customer put it, Variation Designer Advanced “answers literally thousands of questions that we could only guess at previously”.

Includes all capabilities in Premium edition, plus:

Hierarchical Monte Carlo

Hierarchical Monte Carlo

Full chip memory statistical verification

Request a Variation Designer 4 Demo

The best way to discover Variation Designer 4 is to get a personalized demo from one of our expert applications engineers. We’re happy to walk you through the key capabilities and answer any questions you may have.

Request a Demo