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SolidoSTAT: 2nd Generation Statistical Variation Design Tool

Statistical variation causes product failure. Analog/mixed-signal, custom digital and memory IC designers are squeezed by aggressive product cycles, low supply voltages, low power and increasing variation. The unspoken truth is that most products tape-out with serious variation issues. How do you find the source of failure? What should you change in the design to fix it? Products suffer from low margin and delays in time-to-market.

Process technologies and circuit design techniques have made incredible progress, but tools for coping with variation have not kept pace. Best- and worst-case corners only treat global variation. What about local variation/mismatch, which is often dominant? Monte Carlo simulation is time-consuming and inefficient; surely there is a better solution. Designing for statistical variation needs to be faster and produce better results.

SolidoSTAT is a 2nd generation statistical variation design tool that overcomes the limitations of 1st generation tools like Monte Carlo. With SolidoSTAT, you can quickly analyze failures due to statistical variation, identify design weaknesses, and fix the design, making it robust to statistical variation.

Analyze...

...failures due to statistical variation.

Monte Carlo is too slow. SolidoSTAT finds failures far faster than Monte Carlo, giving you more time to identify and fix problems precisely. Using 2nd generation sampling techniques such as Latin Hypercube Sampling, Tail Sampling™, Run-Time Feedback and True Corners™ discovery, SolidoSTAT efficiently analyzes your design under the most important process conditions. Efficiency gains for typical designs range between 10x and 1,000x. This means less time waiting for results, and better use of simulator licenses and compute resources.

Identify...

...weaknesses in the design.

Monte Carlo doesn’t identify the cause of failures. SolidoSTAT goes beyond the histograms and polynomial response surface models used in 1st generation tools, pinpointing key weaknesses that cause design failure and providing guidance for fixing them. Unlike other tools, confidence intervals are provided with results, instead of presenting best guesses as fact. SolidoSTAT identifies problematic sources of variation, critical devices, and limiting environmental conditions, so that you can focus on fixing problems rather than finding them.

Fix...

...the design, making it robust to statistical variation.

With SolidoSTAT, you can fix design failures in minutes instead of days. SolidoSTAT eliminates the need for tedious iteration between design changes and Monte Carlo analysis. Instead, SolidoSTAT lets you fix design weaknesses by rapidly iterating with a small set of True Corners. Critical circuit blocks can be sized for the ideal combination of robustness, performance, and area using detailed block sizing capabilities instead of time-consuming hand analysis. Robust sizing options for the circuit can also be generated automatically. The result is a high-quality, cost-effective, variation-robust design.

Product Benefits:
  • Fix design failures caused by statistical variation
  • Speed up Monte Carlo analysis
  • Improve design quality and profitability



Statistical variation causes failures.
SolidoSTAT is a 2nd generation statistical variation design tool to analyze, identify, and fix design failures caused by statistical variation.

2nd generation statistical variation design is faster and more efficient than Monte Carlo.

Analyze

failures due to statistical variation

Identify

weaknesses in the design

Fix

the design, making it robust to statistical variation
Fast Statistical Sampling:
  • Monte Carlo
  • Latin Hypercube
  • Tail Sampling™
  • True Corners™
  • Run-Time Feedback
  • Parallel Simulation
Mismatch Analysis:
  • Determine how sensitive specific device groups are to mismatch
Statistical Characterization identifies causes of design failure:
  • Critical devices
  • Sources of variation
  • Environmental conditions
Tradeoff Analysis
  • “What-if” tradeoffs between specifications and yield
Block Sizing: quickly size critical circuit blocks for the ideal combination of robustness, performance and area

Rapid Sizing: rapidly size your design with True Corners™, avoiding the need for tedious iteration between design changes and Monte Carlo analysis

Circuit Enhancement: automatically resize your design for statistical variation robustness

  • Find failures far faster than Monte Carlo
  • Reduce simulator license usage
  • Make high-margin yield analysis possible
  • Quickly pinpoint causes of design failure
  • Eliminate tedious, time-consuming “guess and check” design
  • Reduce the risk of project delays and delayed time-to-market
  • Resize key devices to improve performance and yield
  • Fix design failures in minutes versus days
  • Increase margins, reduce area
  • Deliver a variation-robust design

Additional Features

  • Seamless integration with Cadence Virtuoso/Analog Design Environment
  • Works with any simulator (Spectre/Spectre RF, HSPICE, Eldo, and proprietary simulators)
  • Platform LSF and built-in parallel simulation support
  • Matlab / Octave support
  • Flexible command-line interface
  • Works on most Linux and Solaris platforms

Customer Case Studies

DesignTechDevices
Bandgap Reference65nm Foundry350
Sigma-delta ADC Opamp65nm Foundry100
Refgen Amplifier65nm Foundry55
Voltage Regulator65nm IDM600
5-GHz VCO Oscillator90nm IDM48
Variable Gain Amplifier65nm IDM1350
Driver Circuit65nm IDM650
Sense Amplifier130nm Foundry9
ADC IP Block90nm Foundry3000
Shift Register130nm IDM230
LDO Voltage Regulator65nm Foundry300
Telescopic Opamp90nm IDM27
SAR Comparator / Pre-amp65nm Foundry94

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SolidoSTAT Awards:

SolidoSTAT is on the 2007 EDN Hot 100 list
SolidoSTAT named in EDN Hot 100 Products of 2007