By HIRATA Morihisa ・SHIMIZU Takashi ・YAMADA Kenta
NEC Electronics Corporation

Abstract

Advancement in the microfabrication of semiconductor chips has made the variations and layout-dependent fluctuations of transistor characteristics noticeable. It is necessary to develop a design technique that can predict the above phenomena and their effects from the design stage, in order to exploit the maximum performance of transistors and implement high-performance LSIs at low costs. This paper is intended to introduce the efforts made by NEC Electronics for designs considering variations and layout dependence.

Full paper

By Professor Asen Asenov , EE Times Europe, 04/14/2009

Original Article: link

For many years great swathes of the semiconductor industry tried to hide their heads in the sand and ignore the messages coming from research establishments concerning the importance of CMOS statistical variability introduced by the discreteness of charge and matter.

First they completely ignored the problem then they tried to hide it. Now that statistical variability is finally entering the public domain, it’s set to hit the fabless and chipless design companies like a steam hammer.

Thankfully several events coincided in 2008 to challenge the status quo. The big CMOS and electronic device conferences such as the VLSI Technology Symposium, and IEDM were flooded with papers solely focused on the issue of statistical variability in 45-nm and 32-nm technology devices. Statistical variability lay at the heart of special sessions focused on the interaction between technology and design. TSMC replaced the traditional ‘total corners’ with ‘global corners’ and started to advise its customers to superimpose statistical Monte Carlo simulations on top of the global corners to capture the effect of statistical variability in design.

The 2008 ‘update’ of the International Technology Roadmap for Semiconductors (ITRS) also introduced drastic changes compared to the 2007 edition. Some of the most important changes were motivated by the specter of statistical variability in CMOS. The former disparity between the number in nanometers identifying the technology generation (which itself is now divorced from the definition of the half-pitch and has become a purely commercial pointer) and the physical gate length, present in the 2007 ITRS edition, practically disappears at the 22-nm technology generation in the 2008 ITRS update. This is to a great extent motivated by the fact that statistical variability almost ‘explodes’ with the previous prescription for substantial over-scaling of physical device dimensions. In addition, research into new gate stack materials and new device architectures has been mainly motivated by the drive to improve device performance – but not any more. One of the main driving forces behind the introduction of metal gate technology, fully depleted silicon-on-insulator and FinFET devices has been the promise of a reduction in statistical variability.

On top of statistical variability, problems relating to statistical aspects of reliability are looming that will reduce the life-span of contemporary circuits from tens of years to one or two years, or less in the near future. In combination with random discrete dopants, which are the dominant source of statistical variability, the statistical nature of discrete defect charges associated with hot electron degradation and negative bias temperature instability (NBTI) result in relatively rare but anomalously large transistor parameter changes, leading to loss of performance or circuit failure. This is already a fundamental problem in flash and SRAM memories and starts to reduce dramatically the lifetime of digital chips. The irony is that some of the technology innovations, such as the introduction of high-k/metal gate stacks in 45-nm technology generation, which help reduce statistical variability, may in themselves become a reliability time bomb.

First of all the high-k dielectric has lower quality and higher density of fixed/trapped charges. The p-channel high-k transistors are more susceptible to NBTI which can cause an increase in statistical variability with aging. This problem is exacerbated by the creeping positive bias-temperature instability (PBTI) in n-channel high-k transistors which was insignificant in their silicon dioxide gate stack counterparts.

The realization that there is no escape from statistical variability and reliability forces designers to think outside of the box and to find innovative solutions. Such solutions have to cope, not only with the fact that at the moment of fabrication transistors will have a broad statistical variation in their parameters but that during the useful lifetime of the chips aging will cause variability to increase and time to failure will become shorter and shorter if no design countermeasures are implemented.

The urgent need to find design-level solutions to the variability and reliability problems was highlighted in the first call for proposals of the European Nanoelectronics Initiative Advisory Council (ENIAC) Joint Technology Undertaking (JTU) issued in April 2008. As a result a project called MODERN was funded by the European Commission in 2009.

In addition, the National Microelectronics Institute (NMI), the trade association representing the semiconductor industry in the U.K. and Ireland, in collaboration with the U.K.’s nanoCMOS Consortium, is to host its second international conference on CMOS variability, May 12 and 13 2009 at the IET, Savoy Place, London.

Aimed at chip designers, technology developers, wafer foundries and EDA tool vendors, ICCV 2009: “Living with Variability” is set to explore the impact of CMOS variability and how it can be managed at 45-nm and below. Sessions will introduce the issues, discuss the options and share techniques for meeting the challenges of CMOS variability head-on.

The issue of statistical variability in CMOS is being pulled kicking and screaming out of the closet – for all our sakes it’s not before time!

What do you think? Leave your comments below:

Helping chip design and process development move forward

By Ron Wilson, Executive Editor — EDN, 6/26/2008

Original Article: link

As the pivotal player in the CMOS-foundry industry, TSMC (Taiwan Semiconductor Manufacturing Co) occupies the leading edge not only in advanced-process market share, but in process development and the rapidly evolving art of building relationships between foundry engineers and chip-design teams. TSMC’s vice president of research and development, Jack Sun, is in the perfect place to watch both parties in this increasingly complex dance as they strive to outmaneuver the growing complexity of CMOS processes. EDN asked Sun what he sees as the foremost problem facing the foundry-design relationship today.

Sun answered quickly. “The primary problem today, as we take 40 nm into production, is variability,” he says. “There is only so much the process engineers can do to reduce process-based variations in critical quantities. We can characterize the variations, and, in fact, we have very good models today. But they are time-consuming models to use. So, most of our customers still don’t use statistical-design techniques. That means, unavoidably, that we must leave some performance on the table.”

Sun went on to describe a number of measures that TSMC engineers and customers are taking to reduce the amount of performance chip designers must give up to guard-banding. To begin with, he says, TSMC has consistently made decisions in choosing its process architectures to make things simpler for chip designers. One such decision was the choice—despite considerable capital and development investment—to move to immersion lithography. Immersion has significant benefits for the foundry. But it also means that TSMC can deliver—other variables being equal—more consistent shapes and accurate lithography simulation. “We can pretty accurately predict the actual shapes of features on the silicon now,” Sun says. “That means that extraction tools can more accurately predict transistor performance [and] circuit and parasitic impedances. And we don’t have to leave too much on the table to allow for unexpected variations in shapes and dimensions.”

Another key choice, Sun maintains, was the decision to stay with a conventional silicon-gate, silicon-oxide-dielectric gate stack. “We were able to stay with a structure our customers are used to,” Sun says, “and still achieve leadership in power density. Our non-high-k process is rivaling competitive high-k processes.”

But this choice meant that the foundry had to take other steps to increase performance. Sun says that the 40-nm process required scrupulous design work to eliminate excess gate capacitance, further wrestling with contact resistance, and a substantial increase in strain on the channels. “At this point, we are about running out of room for strain structures on the transistor,” Sun admits. Feature density and the fact that the impact of strain on channel mobility is orientation-dependent have required TSMC to require fixed-pitch patterns in dense areas and to enforce unidirectional channel orientation.

Another key area in making the process usable for chip designers is modeling—creating not just accurate models, but also the process controls that reduce variations enough to make the models meaningful. Sun says that baseline transistor models are still adequate—at least for the 40-nm, baseline transistor models. Substrate modeling, however, creates extremely complex nets and requires a huge amount of silicon validation, making it a more complex issue.

Sun highlights the issue of advanced process controls. “TSMC uses both feed- back and feedforward control loops and gathers a huge amount of data. We do a lot of, if you will, data mining to find the best knobs to tweak to control process variables,” he says. “We have so much experience with this now that we are tantalizingly close to being able to do an expert system for process centering.” In one case, TSMC had established an integrated link between its advanced process-control system and the chip-design partner’s database. “It’s a new concept we are trying,” he explains. “For most partners, we provide data in the form of process sensitivities, so the partners can update their test procedures to look for the things that we know can vary.”

In the absence of statistical tools, TSMC must also work to develop process corners that accurately reflect the vastly more complex patterns of variations happening across wafer lots. “We try to find ways to lump parameters together to simplify the corners,” Sun says. “But there are, for instance, layout-dependent stress effects. It’s a pain you have to live with. The best we can do is to provide accurate Spice models and restrictive design rules that will reduce the variations.”

The ultimate weapon in controlling process variations, Sun emphasizes, is not some magic bullet to make the variations go away or magic tool to make them invisible but, rather, a close partnership with design teams to allow them to design with the variations.

“Early adopters—companies like Qualcomm and Altera, which are already on 40 nm—have very early and deep collaboration with the process team,” Sun says. “As the process matures, we see a second wave of design teams. These teams still require collaboration, maybe for specific customized features, but otherwise they are working with a proven process and far less uncertainty.”

Even though this phased approach describes most collaborations, RF and precision analog designs still represent something of an exception. “RF and analog design have art to them,” he says. “The degree of collaboration that actually happens between the design team and its foundry depends on the sensitivity of the design team.” Some designers want all the help they can get, Sun suggests, whereas others don’t want anyone from outside the team to see—let alone participate in—what is happening within the design team’s inner circle. “This [reluctance] can really hinder collective learning,” Sun says, “but you have to respect the needs of the designers for differentiation. I think, though, that there is room to improve the model while respecting that. A lot of designers have their own secret sauce. But if the collaboration is not open, you end up leaving the optimizations undone.”

What do you think? Leave your comments below:

By Paul McLellan, 3/31/2009

Original Article: link

I like to say that “you can’t ignore the physics any more” to point out that we have to worry about lots of physical effects that we never needed to consider. But “you can’t ignore the statistics any more” would be another good rallying cry.

In the design world we like to pretend that the world is pass/fail. If you don’t break the design rules your chip will yield. If your chip timing works at the worst case corner then your chip will yield (yes, you need to look at other corners too).

But manufacturing is actually a statistical process and isn’t pass/fail at all. One area that is getting worse with each process generation is process variability especially in power and timing. If we look at a particular number such as the delay through a nand-gate then the difference between worse-case and typical is getting larger. The standard-deviation about the mean is increasing. This means that when we move from one process node to the next, the typical time improves by a certain amount but the worst-case time improves by much less. If we design to worst-case timing we don’t see much of the payback from the investment in the new process.

An additional problem is that we have to worry about variation across the die in a way we could get away with ignoring before. In the days before optical proximity correction (OPC) the variation on a die were pretty much all due to things that affected the whole die: the oxide was slightly too thick, the reticle was slightly out of focus, the metal was slightly over-etched. But with OPC, identical transistors may get patterned differently on the reticle, depending on what else is in the neighborhood. This means that when the stepper is slightly out of focus it will affect identical transistors (from the designer’s point of view) differently.

Treating worst-case timing as an absolutely solid and accurate barrier was always a bit weird. I used to share an office with a guy called Steve Bush who had a memorable image of this. He said that treating worse case timing as accurate to fractions of a picosecond is similar to the way the NFL treats first down. There is a huge pile of players. Somewhere in there is the ball. Eventually people get up and the referee places the ball somewhere roughly reasonable. And then they get out chains and see to fractions of in inch whether it has advanced ten yards or not.

Statistical static timing analysis (SSTA) allows some of this variability to be examined. There is a problem in static timing of handling reconvergent paths well, so that you don’t simultaneously assume that the same gate is both fast and slow. It has to be one or the other, even though you need to worry about both cases.

But there is a more basic issue. The typical die is going to be at a typical process corner. But if we design everything to worst case then we are going to have chips that actually have a much higher performance than necessary. But now that we care a lot about power this is a big problem: they consume more power than necessary giving us all that performance we cannot use. There has always been an issue that the typical chip has performance higher than we guarantee, and when it is important we bin the chips for performance during manufacturing test. But with increased variability the range is getting wider and when power rather than timing is important, too fast is a big problem.

One way to address this is to tweak the power supply voltage to slow down the performance to just what is required, along with a commensurate reduction in power. This is called adaptive voltage scaling (AVS). Usually the voltage is adjusted to take into account the actual process corner, and perhaps even the operating temperature as it changes. Once this is done then it is possible to bin for power as well as performance. Counter intuitively, the chips at the fastest process corner may well be the most power thrifty since we can reduce the supply voltage the most.

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