By Daniel Nenni, 08/05/2009
Original Article: link
Hands down, the most popular blogs I have written are on yield, TSMC yield of course. It started with TSMC’s Dr. Jack Sun interview, and more recently Blogging from Taiwan: TSMC 40nm Yield . So in the name of views and maintaining my massive blog ego, here is another one on TSMC yield!
By far the most revealing session at the Design Automation Conference (DAC) last week was on Design for Manufacturing (DFM) entitled “DFM: Band-Aid or Competitive Weapon”. I first wrote about DFM in an EETimes article Taking the pain from design for manufacturability circa 2003, suggesting that companies who don’t design for manufacture will be Desperate For Money. John Cooley shortsightedly tagged DFM as Design For Marketing.
Two important quotes from the DFM session that directly support my writings on DFM and yield:
“DFM is many things to many people,” said Mark Redford, VP Advanced Technology Development at Cambridge Silicon Radio, (Cambridge, U.K.). “DFM tools need to be part of the design flow and foundries need to provide statistically valid data that covers the layout styles of their product portfolio.”
“We should also discriminate hard to manufacture parts of chips like analog portions from the relative easier digital parts of an SoC in order to tackle the process variability challenge,” concluded TSMC’s Kuo Wu.
An even more telling yield quote (unscripted) came from TSMC’s Dr Mark Liu at the end of the most recent earnings call:
In this generation (40nm), what we find, what’s important is the design, layout styles because in our products, we do see the design has a — because a different product has a different yield showing and it ranged quite widely and we find that for those products, the yield is low is mainly because of the design layout dependence. What we call Design for Manufacturing. That is in plain English is when the design cannot be completely described by the design rule……
This is a process variation problem, or, equivalently, the required trade offs between performance, power, area, and yield. Fortuitously, a new book hit the shelves of the Springer booth at DAC which addresses the problem in detail: “Variation-Aware Analog Structural Synthesis”. Even better, three of the authors were at DAC and it was my pleasure to meet them, (1) Trent McConaghy is co-founder and Chief Scientific Officer of Solido Design Automation Inc. He was also co-founder and Chief Scientist of Analog Design Automation Inc., which was acquired by Synopsys Inc. in 2004. (2) Pieter Palmers, Director of Application Engineering of Mephisto Design. (3) Prof. Georges Gielen of K.U. Leuven, who is renowned for his work in analog modeling and design, in addition serving as chair of DATE, of ICCAD, and on DAC’s executive committee.
Transistors may be shrinking, but atoms aren’t. So now it actually matters when even a few atoms are out of place. So process variations, whether they are statistical, proximity, or otherwise, have got to be thoughtfully accounted for, if we are to achieve low-power, high-performance, and high yield design goals. This book describes CAD tools for designers to manage and gain insight into the relation among analog circuit topology choices, device sizes, performances and variations.
Unfortuitously, the book lists for $129 USD, which is beyond a Blogger’s pay grade, so I will have to wait for my complimentary autographed copy, or you can contact Solido.
