TSMC’s use of Solido solutions for Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes
Duration: 55 minutes
Request to View and Discuss the Webinar Live with a Solido AE:
Variation effects have an increasing impact on advanced process nodes, and at each, new sources of variation must be considered. Furthermore, increased competition is forcing tighter design margins to make high-performance, low-power, low-cost products. Designers must now do more variation analysis than ever to achieve these tighter margins, using advanced variation-aware technology for speed, accuracy and coverage to deliver competitive chips on schedule. This webinar will discuss on how TSMC manages variation-aware design in memory and standard cell with TSMC advanced processes using Solido’s new Variation Designer 4.
IC Designers • Design Managers • CAD Managers • Directors
What the Audience Will Learn:
Variation-aware design techniques for high-performance, low-power, low-cost products for memory and standard cell.
Technical Marketing Manager, TSMC
Jacob Ou is a technical manager at TSMC. He has more than 8 years of experience in simulators, PDK, router and worldwide customer support. His role at TSMC is managing EDA-related projects with the engineering team addressing simulation and STA challenges at the most advanced nodes. He received his MSEE from National Cheng Kung University.
VP Customer Applications, Solido
Kristopher Breen is Vice President, Customer Applications at Solido Design Automation. He has over 11 years of experience managing the development, deployment, and support of variation-aware design and verification solutions for customers worldwide. Breen is also co-author of Variation-Aware Design of Custom Integrated Circuits: A Hands-On Field Guide. He received his M.Sc. in Electrical and Computer Engineering from the University of Alberta, Canada.